1. Field of the Invention
This invention relates to a method for fabricating multilevel interconnects, and more particularly, to a method for preventing the occurrence of poisoned vias and trenches.
2. Description of Related Art
A dual damascene process is a technique, which imbeds interconnects into an insulator, includes forming an insulator, planarizing and patterning the insulator to form trenches and via holes, and filling the trenches and via holes with metal to form conducting wires and via plugs. A final chemical mechanical polishing process is then performed to planarize the surface of a device. Because a dual damascene process prevents the occurrence of overlay error and process bias of a conventional metalization process, it has been widely applied on semiconductor processes to improve the reliability of devices.
FIGS. 1A through 1D are cross-sectional views showing a conventional method for fabricating a dual damascene structure.
Referring to FIG. 1A, an etching stop 104, and then a dielectric layer 106 are formed on a provided substrate 100 in sequence, wherein the substrate 100 contains a metal layer 102. A planarization process is performed on the dielectric layer 106 to polish the dielectric layer 106 to a desired thickness, the depth of desired via plugs. Then, another etching stop 108 and dielectric layer 110 are formed on the dielectric layer 106 in sequence, and planarized, wherein the thickness of the dielectric layer 110 equals to the thickness of the conducting wires of the dual damascene structure to be formed in a follow-up process. The dielectric layers 106 and 110 typically include silicon oxide formed by a chemical vapor deposition process. The etching stop 104 includes silicon nitride formed by a chemical vapor deposition process. Another etching stop 108 includes silicon-oxy-nitride formed by a chemical vapor deposition process.
Referring next to FIG. 1B, the dielectric layer 110 is patterned to from openings 112, wherein the positions of the openings 112 are corresponding to the positions of the metal layer 102 underneath. Generally, the openings 112 are formed by first depositing and patterning a photoresist layer (not shown in figure), performing an etching process on the dielectric layer 110 by using the patterned photoresist layer as a mask and using the etching stop 108 as etching end point, and then, removing the photoresist layer.
Referring to FIG. 1C, conventionally, a portion of the etching stop 108 that is exposed within the openings 112 is removed for transferring a pattern onto the etching stop 108. By using another patterned photoresist layer (not shown in figure) and the patterned etching stop 108 as masks, a portion of the dielectric layer 106 beneath the openings 112 and a portion of the dielectric layer 110 around the openings 112 are removed to form via holes 116 and trenches 114. Then, by using an etching stop 108 as a mask, a portion of the etching stop 104 is removed, so that the metal layer 102 is exposed by the via holes 116, the trenches 114 are further widened as well. The trenches 114 and via holes 116 comprise the openings 118 of a dual damascene structure.
Referring next to FIG. 1D, the openings 118 are filled with conductive material to form a dual damascene structure 126. Generally, the dual damascene structure 126 consists of a metal layer 124, such as aluminum, tungsten, or copper, and a barrier/glue layer 122, such as titanium/titanium nitride, wherein the barrier/glue layer 122 is conformal to the openings 118. A planarization process is performed to remove unwanted conductive material from the top of the dielectric layer 110.
As the integration of a semiconductor device is increased, the resistance-capacitance delay regarding to the parasitic capacitance generated by an inter-metal dielectric layer, such as dielectric layers 110 and 106 as shown in FIG. ID, is worsened. Hence, it is common to utilize low-permittivity dielectric to form inter-metal dielectric in a sub-micron semiconductor fabrication process. Conventionally, the low-permittivity dielectric includes organic materials such as spin-on-polymer (SOP), flare, SILK, and parylene, and inorganic materials, such as HSQ and FSG. Since most low-permittivity dielectrics tend toward absorbing moisture, that causes outgassing phenomena during the process of filling conductive material into the openings 118. The outgassing phenomena happening within the dielectric layers further lead to the occurrence of poisoned trenches and vias that degrades the yield and the electrical property of a device.